1. Field of the Invention
The present invention relates to a DMA controller which performs data transfer between a memory and peripheral apparatus by way of a DMA system.
2. Description of the Related Art
In order to speed up data transfer between a memory and peripheral apparatus, a DMA controller is used as dedicated hardware for performing data transfer between the memory and the peripheral apparatus. FIGS. 2 through 7 explain a related art DMA controller. FIGS. 2 and 3 explain DMA transfer from a non-contiguous memory area in rectangular block transfer. FIG. 4 shows an address space used to explain data transfer on a ring buffer. FIG. 5 shows an address space used to explain data transfer on a ring buffer. FIG. 6 is a block diagram showing an example of the configuration of an address generator circuit in a related art DMA controller. FIG. 7 is a block diagram showing an example of a general system LSI which uses a DMA controller (DMAC).
In FIG. 7, a CPU 701 and a DMAC 702 are connected as a bus master to a high-speed bus 711. As a bus slave, a ROM 703, a RAM 704, an SDRAM 706, and a bus bridge 705 are connected to the high-speed bus 711. The bus bridge 705 is located between the high-speed bus 711 and a low-speed bus 712. To the low-speed bus 712 are connected serial apparatus 707, storage media apparatus 708 and a USB apparatus 709.
In FIG. 6, the address generator circuit 601 implements ring buffer transfer and rectangular block transfer in the DMAC 702.
Operation of rectangular block transfer is described below. In case image data is stored on the SDRAM 706 in FIG. 7, the user may wish to import, by way of DMA transfer, part of the image data rather than the entire image to the RAM 704 for processing. Such an image is for example a standby screen on a cell phone or an image of an antenna (indicating the standby state) as part of the screen. In case part of the image data is being transferred as described above, rectangular block transfer is used.
In the DMA transfer from a non-contiguous area in the rectangular block transfer shown in FIGS. 2 and 3, FIG. 3 shows the relationship between an image area 301 and a rectangular area 302 as part of the image area 301, and FIG. 2 shows the structure of the rectangular area 302 in an address space.
To transfer the rectangular area 302 in FIG. 3, DMA transfer is made for the data length L1 of an area which requires DMA transfer (contiguous area) while DMA transfer is not made for the data length L2 of an area which does not require DMA transfer (non-contiguous area) Referring to the address space in FIG. 2, areas such as the areas from address 201 to address 202, from address 203 to address 204, and from address 205 to address 206 are transferred in order to transfer the rectangular area 302.
That is, once the data having the data length L1 from the start address 201 to address 202 is transferred, the area for the data length L2 need not be transferred, so that the transfer address jumps from address 202 to address 203. Similarly, the area having the data length L1 from address 203 to address 204 is transferred then the transfer address jumps from address 204 to address 205. This performs transfer of a rectangular area.
Operation of generating the rectangular address mentioned above in the address generator circuit 601 will be described. Register setting from the CPU 701 to the DMAC 702 sets DMA transfer parameters. In this practice, a start address is set to a register 602, the number of DMA transfers for the contiguous area to a register 606, and the address increment of the non-contiguous area to a register 605.
Next, DMA transfer starts. The value of the register 602 where a start address is set is selected by a multiplexer 610 and set to a register 611 which retains the transfer address output and a register 603 provided to internally reference the transfer address. Then, the value of a register 604 which retains the address increment and the value of the register 603 which retains a transfer address selected by a multiplexer 608 are summed by an adder 609. The resulting value is selected by the multiplexer 610 and set to the register 611 and the register 603 again.
The address increment is 1 in case ordinary addresses are incremented one by one for transfer while it is 4 in case addresses are assigned per eight bits on a 32-bit bus. Assuming a current transfer address as ADC, a next transfer address as ADN and an increment as AI, the expression holds: ADC=ADC+AI.
The value of the register 606 where the number of DMA transfers is set is loaded into a counter 607 at the start of DMA transfer and decrements the counter 607 per DMA transfer cycle. Occurrence of underflow in the counter 607. indicates the end of DMA transfer. In this practice, the multiplexer 608 selects the output of an adder 615 in order to add the address increment of the non-contiguous area and loads the value of the register 606 to the counter 607 again.
The adder 615 sums up the register 603 where the address increment of the non-contiguous area is set and the register 603 where the current transfer address is retained. Assuming the address increment of the non-contiguous area as ADR, the next transfer address ADN is given by the expression ADN=ADC+ADR+AI.
In this case, ADR and AI are summed because the last address in a contiguous area is smaller than the first address of a non-contiguous area by AI and adding the address increment of a non-contiguous area to the last address of a contiguous area makes the last address of the non-contiguous area.
In this way, by switching the selection by the multiplexer 608 to jump to the start address of the next contiguous area, DMA transfer of a rectangular area shown in FIG. 3 is performed.
Operation of a ring buffer is described below. Data from the serial apparatus 707 or the USB apparatus 709 is stored into a memory such as a FIFO inside the serial apparatus 707 or the USB apparatus 709 and transferred to the RAM 704 or the SDRAM 706 by the DMAC 702. In case such contiguous data is sequentially received, a certain range on the RAM 704 may be configured as a ring buffer.
In an address space used to explain data transfer in a ring buffer shown in FIGS. 4 and 5, a numeral 401 denotes the start address of a ring buffer and 402 the end address of the ring buffer.
Data received from the USB apparatus 709 is sequentially stored from the start address 401. Once address 402 is reached, a transfer address is returned to address 401. Similarly, in case data is read from a ring buffer, data is read sequentially from the start address 402, with a transfer address being returned to address 401 once address 402 is reached.
Here, WP is the transfer address of a DMA controller which writes data into memory while RP is the transfer address of a DMA controller which reads data from memory. WP and RP operate in synchronization In FIG. 4, an area M1 is an area where data is written and read, an area M2 an area where data is once written but waiting to be read, an area M3 an area where data is not yet written
FIG. 5 shows a state where a predetermined time has elapsed from the state in FIG. 4 and WP has returned at 402. In an area M4, a second write is complete and a first read has been made but the second write data is not yet read. An area M5 is and area where data is written once and read once. An area M6 is an area where data is written once and waiting for a first read.
In order to perform data transfer to a ring buffer, a related art DMA controller comprises a register 612 for specifying the start address of a ring buffer, a register 613 for specifying the end address of the ring buffer; and a comparator for comparing a register 603 which retains the current transfer address and the register 613, wherein a multiplexer 610 selects the register 612 which retains the start address of the ring buffer (refer to for example the Japanese Patent Laid-Open No. 4458/1994),
In the related art method, in order to perform DMA transfer to a ring buffer, it is necessary to add circuits dedicated to the ring buffer such as a start address register and an end address register for the ring buffer as well as a comparator.
A general-purpose DMA controller must often support transfer of a non-contiguous area such as a rectangular area mentioned above. In order to support all the requests for additional features to such a general-purpose DMA controller, the circuit required is complicated as shown in FIG. 6 thus resulting in a larger circuit scale. This problem is eminent especially in case a plurality of peripheral devices and a plurality of channels are provided to perform DMA transfer.